Wikipedia / NEAT chipset
Wikipedia / NEAT chipset
The NEAT chipset (the acronym standing for "New Enhanced AT") is a 4 chip VLSI implementation (including the 82C206 IPC) of the control logic used in the IBM PC compatible PC/AT computers. It consists of the 82C211 CPU/Bus controller, 82C212 Page/Interleave and EMS Memory controller, 82C215 Data/Address buffer, and 82C206 Integrated Peripherals Controller (IPC). NEAT, official designation CS8221, was developed by Chips and Technologies.
History
The NEAT chipset descended from the first chipset that C&T had developed for IBM XT-compatible systems, which is based around the 82C100 "XT controller" chip. 82C100 incorporates the functionality of what had been, until its invention, discrete TTL chips on the XT's mainboard, namely:
8284 clock generator
8255 parallel I/O interface
8255 Programmable Peripheral Interface (PPI)
DRAM/SRAM controller
XT Keyboard controller
IBM PC compatibility is provided by CT's 82C206 Integrated Peripheral Controller (IPC), introduced by C&T in 1986. This chip, like its predecessor the 82C100, provides equivalent functionality to the TTL chips on the PC/AT's mainboard, namely:
82284 clock generator
74LS612 Memory Mapper chip
NEAT CS8221's predecessor, called CS8220, requires five chips (buffers and memory controllers) for a virtually complete motherboard, while NEAT requires four, and added support for separate ISA bus clocks. The eventual successor to the NEAT chipset, 82C235 Single Chip AT (SCAT), amalgamates all of the chips of the NEAT chipset into a single chip.
Other manufacturers
Other manufacturers produced equivalent chips. OPTi, for example, produced a two-chip "AT controller" chipset comprising the OPTi 82C206 and 82C495XLC, which is found in many early 80486 and Pentium AT-compatible machines. The OPTi 82C206 is pin and function compatible with CT's 82C206. The 82C495XLC incorporates the additional memory controller and shadow RAM support.
References