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Wikipedia / Subtractor

In electronics, a subtractor is a digital circuit that performs subtraction of numbers, and it can be designed using the same approach as that of an adder. The binary subtraction process is summarized below. As with an adder, in the general case of calculations on multi-bit numbers, three bits are involved in performing the subtraction for each bit of the difference: the minuend), subtrahend.

  1. ,

where ⊕ represents exclusive or.

Subtractors are usually implemented within a binary adder for only a small cost when using the standard two's complement notation, by providing an addition/subtraction selector to the carry-in and to invert the second operand.

  1. (definition of two's complement notation)

Half subtractor

The half subtractors can be designed through the combinational Boolean logic circuits [2] as shown in Figure 1 and 2. The half subtractor is a combinational circuit which is used to perform subtraction of two bits. It has two inputs, the minuend and subtrahend on the diagram is given by

  1. .

This is an important distinction to make since subtraction itself is not commutative is calculated using an XOR gate which is commutative. The truth table for the half subtractor is:Using the table above and a Karnaugh map:

  1. .

Consequently, a simplified half-subtract circuit, advantageously avoiding crossed traces in particular as well as a negate gate is: 

     X ── XOR ─┬─────── |X-Y|,  is 0 if X equals Y, 1 otherwise
        ┌──┘   └──┐  
     Y ─┴─────── AND ── borrow, is 1 if Y > X, 0 otherwise

where lines to the right are outputs and others (from the top, bottom or left) are inputs.

Full subtractor

The full subtractor is a combinational circuit which is used to perform subtraction of three input bits.

The truth table for the full subtractor is:Therefore the equation is:

See also

References

  1. Foundations Of Digital Electronics by Elijah Mwangi

  2. Beltran, A.A., Nones, K., Salanguit, R.L., Santos, J.B., Santos, J.M., & Dizon, K.J. (2021). Low Power NAND Gate–based Half and Full Adder / Subtractor Using CMOS Technique.