Wikipedia / Ling adder
Wikipedia / Ling adder
In electronics, a Ling adder is a particularly fast binary adder designed using H. Ling's equations. Samuel Naffziger of Hewlett-Packard presented an innovative 64 bit adder in 0.5μm CMOS based on Ling's equations at ISSCC 1996. The Naffziger adder's delay was less than 1 nanosecond, or 7 FO4.
Equations
Ling adder, architecture Skllansky, radix-2, 4-bit
'--- Step 0 ------------ Warning ---------------------------------------
P00 = A0 OR B0 '1dt, Initial only CLA & Ling Propagate (not in PPA)
G00 = A0 AND B0 '1dt, Initial CLA & Ling & PPA Generate
D00 = A0 XOR B0 '1dt, Only Ling Initial half bit generate (P0 in PPA)
P10 = A1 OR B1 '1dt
G10 = A1 AND B1 '1dt
D10 = A1 XOR B1 '1dt
P20 = A2 OR B2 '1dt
G20 = A2 AND B2 '1dt
D20 = A2 XOR B2 '1dt
P30 = A3 OR B3 '1dt
G30 = A3 AND B3 '1dt
D30 = A3 XOR B3 '1dt
'--- Step 1, Ling Propagate and Generate ------
LG01 = G00 '1dt
LG11 = G10 OR G00 '2dt
LP11 = P10 '1dt, Sklansky architecture
LG21 = G20 '1dt, Sklansky architecture
LP21 = P20 AND P10 '2dt
LG31 = G30 OR G20 '2dt
'--- Step 2, Ling PseudoCarry (H) ---------------------------
H0 = LG01 '1dt
H1 = LG11 '2dt
H2 = LG21 OR (LP11 AND LG11) '4dt TTL, Sklansky architecture
' 1dt 1dt 2dt
H3 = LG31 OR (LP21 AND LG11) '4dt TTL
' 2dt 2dt 2dt
'--- Sum -----------------------------------------
S0 = (D00 ) '1dt
S1 = (D10 AND 1-H0) OR ((D10 XOR P00) AND H0) '4dt TTL
S2 = (D20 AND 1-H1) OR ((D20 XOR P10) AND H1) '5dt TTL
S3 = (D30 AND 1-H2) OR ((D30 XOR P20) AND H2) '7dt TTL
S4 = (( P30) AND H3) '5dt TTL, S4=C4=Cout
http://andserkul.narod.ru/R2LSK4.basLing Adder, architecture Sklansky, Binary, Radix-2, 4-bitandserkul.narod.ruTXTLing adder, architecture Kogge-Stone, radix-2, 4-bit
'--- Step 0 ------------ Warning ---------------------------------------
P00 = A0 OR B0 '1dt, Initial only CLA & Ling Propagate (not in PPA)
G00 = A0 AND B0 '1dt, Initial CLA & Ling & PPA Generate
D00 = A0 XOR B0 '1dt, Only Ling Initial half bit generate (P0 in PPA)
P10 = A1 OR B1 '1dt
G10 = A1 AND B1 '1dt
D10 = A1 XOR B1 '1dt
P20 = A2 OR B2 '1dt
G20 = A2 AND B2 '1dt
D20 = A2 XOR B2 '1dt
P30 = A3 OR B3 '1dt
G30 = A3 AND B3 '1dt
D30 = A3 XOR B3 '1dt
'--- Step 1 ----------------------------
LG01 = G00 '1dt, Ling Generate
LP11 = P10 AND P00 '2dt, Ling Propagate, Kogge-Stone architecture
LG11 = G10 OR G00 '2dt
LP21 = P20 AND P10 '2dt
LG21 = G20 OR G10 '2dt, Kogge-Stone architecture
LG31 = G30 OR G20 '2dt
'--- Step 2, Ling PseudoCarry ----
H0 = LG01 '1dt
H1 = LG11 '2dt
H2 = LG21 OR (LP11 AND LG01) '4dt TTL, Kogge-Stone architecture
' 2dt 2dt 1dt
H3 = LG31 OR (LP21 AND LG11) '4dt TTL
' 2dt 2dt 2dt
'--- Sum -----------------------------------------
S0 = (D00 ) '1dt
S1 = (D10 AND 1-H0) OR ((D10 XOR P00) AND H0) '4dt TTL
S2 = (D20 AND 1-H1) OR ((D20 XOR P10) AND H1) '5dt TTL
S3 = (D30 AND 1-H2) OR ((D30 XOR P20) AND H2) '7dt TTL
S4 = (( P30) AND H3) '5dt TTL, S4=C4=Cout
http://andserkul.narod.ru/R2LKS4.basLing Adder, architecture Kogge-Stone, Binary, Radix-2, 4-bitandserkul.narod.ruTXTReferences
External links
H. Ling, "High Speed Binary Parallel Adder", IEEE Transactions on Electronic Computers, EC-15, p.799-809, October, 1966.
H. Ling, "High-Speed Binary Adder", IBM J. Res. Dev., vol.25, p.156-66, 1981.
R. W. Doran, "Variants on an Improved Carry Look-Ahead Adder", IEEE Transactions on Computers, Vol.37, No.9, September 1988.
N. T. Quach, M. J. Flynn, "High-Speed Addition in CMOS", IEEE Transactions on Computers, Vol.41, No.12, December, 1992.
S. Naffziger, "High Speed Addition Using Ling's Equations and Dynamic CMOS Logic", U.S. Patent No. 5,719,803, Issued: February 17, 1998.
G. Dimitrakopoulos, D. Nikolos, "High-Speed Parallel-Prefix VLSI Ling Adders", IEEE Transaction on Computers, Vol.54, No.2, February, 2005.