In a central processing unit (CPU), a status register, flag register, or condition code register (CCR) is a register that stores flagss (bits) indicating the processor state and results of operations. Examples of such registers include the FLAGS register in x86 CPUs, the program status word (PSW) register in IBM's System/360 through z/Architecture, the application program status register (APSR) in 32-bit ARM architectures, and the NCSV system register in AArch64.

The status register contains information about the state of the processor. Individual bits are implicitly or explicitly read or written by the machine code instructions executing on the processor. The status register lets an instruction take action contingent on the outcome of a previous instruction.

Typically, some of the flags in a status register are modified as a result of arithmetic and bit manipulation operations performed by the arithmetic logic unit (ALU). For example, a Z status bit may be set if the result of an operation is zero or cleared if it is nonzero. A string instruction may modify a status flag to indicate whether it terminated due to finding a match or reaching the end of the string. Some flags are used later by conditional instructions to control program execution.

Some instruction set architectures (ISAs) do not use a dedicated flag register, such as the MIPS and Alpha; others do not implicitly set or read flags. Such machines either do not pass implicit status information between instructions or pass it in a general purpose register.

A status register may have additional fields such as privilege flags, interrupt enable bits, and other types of information. During an interrupt, the status of the currently executing thread can be preserved by storing the current value of the status register (along with the program counter and other active registers) to the machine stack or other memory.

Common flags

Here is a list of CPU status register flags commonly implemented in modern processors:

Other flags

On some processors, the status register might contain flags such as these:

Designs without arithmetic flags

Status flags enable an instruction to act based on the result of a previous instruction. In pipelined processors, such as superscalar and speculative processors, this can create hazards that slow processing or require extra hardware to work around them.

Some very long instruction word processors dispense with the status flags. A single instruction both performs a test and indicates on which outcome of that test to take an action, such as Compare a with b and Jump to c if Equal. The result of the test is not saved for subsequent instructions.

Another alternative to the status register is for processor instructions to deposit status information in a general-purpose register when the program requests it. MIPS, AMD 29000, DEC Alpha, and RISC-V are examples of architectures that provide comparison instructions that store the comparison result in a general-purpose register, as a single bit or a numeric value of 0 or 1. Conditional branches act based on the value in the general-purpose register.

Usually, comparison instructions test equality or signed/unsigned magnitude. To test for other conditions, a program uses an equivalence formula. For example, MIPS has no "carry bit" but a program performing multiple-word addition can test whether a single-word addition of registers overflowed by testing whether the sum is lower than an operand:

The sltu instruction sets tmp to 1 or 0 based on the specified comparison of its two other operands. (Here, the general-purpose register tmp is not used as a status register to govern a conditional jump; rather, the possible value of 1, indicating carry from the low-order addition, is added to the high-order word.)

This scheme becomes less convenient when adding three or more words, as there are two additions when computing b + c + tmp, either of which may generate a carry, which must be detected with two sltu instructions. Fortunately, those two carries may be added to each other without risk of overflow, so the situation stabilizes at five instructions per word added.

See also

• Control register

• CPU flags in x86 ISA

• Flag field

References