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Wikipedia / Body effect

The body effect (also known as substrate bias effect) is an undesired second-order effect present in field-effect transistors (MOSFET) that describes the change in transistor's threshold voltage) resulting from a potential difference between the source and the bulk (substrate) terminals. While ideal first-order MOSFET models assume that the source and bulk are tied to the same potential, in many integrated circuit topologies the source voltage varies dynamically while the substrate is kept at a global reference potential. This voltage difference alters the internal electrostatic balance of the device, strongly modifying the device biasing condition, switching characteristics and amplification capabilities.

Basic principle

The operation of any metal-oxide-semiconductor field-effect transistor relies on the precise modulation of energy bands). This phenomenon is called field effect and enables the doping is actually used to modulate the bands inside the semiconductor, while part of it drops across the oxide and depends on the amount of fixed charge exposed in the substrate due to the creation of the inversion layer.

, the depletion layer beneath the gate oxide widens, increasing the amount of uncompensated doping ions exposed by the field effect, and therefore threshold voltage condition.

Physical framework

In an enhancement-mode nMOS device, concerning the source-to-bulk voltage, it is possible to establish two possible conditions:

  • )

  • )

) is usually neglected as a valid operating regime as it generally fails to prevent currents flowing in the source-bulk and drain-bulk p-n junctions, therefore impairing the correct MOSFET operation. An equivalent argument can also be derived for the dual pMOS device.

Neutral condition (VSB= 0)

) and when the drain and source terminals are cosidered at same electrostatic potential), a single and constant Fermi level) exists across the entire substrate-channel structure. To establish an electron conduction channel between the source and drain, the energy bands must bend downward at the semiconductor-oxide interface. This so called threshold condition for inversion, for which the density of electrons at the interface reaches the same doping value of holes in the bulk, is obtained when the surface potential satisfies the following equation:

 is called bulk Fermi potential, and defined as:

is the Boltzmann constant is the absolute temperature expressed in Kelvin is the elementary charge is the intrinsic carrier concentration of the semiconductor.

, can be expressed as:

is the flat band voltage is the depletion charge density exposed in the substrate (depletion layer is defined as the threshold voltage holds.

Reverse body biasing (VSB > 0)

When a positive source-to-bulk voltage is applied, the p-n junction formed by the p-type substrate and the n+ source region goes deeper into reverse-bias condition. This external bias drives the system out of thermodynamic equilibrium, causing the unique Fermi level to split into two distinct quasi-Fermi levels:

  • : the quasi-Fermi level for holes, anchored to the potential of the substrate.

  • : the quasi-Fermi level for electrons, which is pulled down by the higher potential of the source.

Since the source potential is higher with respect to the bulk, the energy level. In this circumstance, the bands must bend significantly more than they did at equilibrium to "chase" the shifted quasi-Fermi level of the source and in this way populate the conduction band defined by the more general equality:

Given the higher surface potential needed, the amount of charge collected at the oxide-semiconductor interface becomes:

as:

is the general expression of the threshold voltage of the device in presence of body biasing.

, with no actual assumption regarding the doping profile present in the bulk.

Threshold voltage

For a uniformly doped substrate, the dependence of the threshold voltage on the source-to-substrate voltage can be analytically modeled by the body effect equation

is the body effect coefficient expressed as:

is the permettivity of silicon.

This formulation highlights how geometric and technological parameters dictate the influence of the body on the threshold voltage. Specifically, it demonstrates that the body effect scales with:

  • ): a higher substrate doping increases the depletion charge, potentially intensifying the body effect;

  • , a thinner oxide increases the gate control on the channel, thereby shielding it from unwanted body variations.

Small-signal model

In analog circuits) in a manner similar to the gate terminal. This behavior can be modeled through a small-signal equivalent circuit by introducing a voltage controlled current source driven by the body-source voltage. More precisely, it is possible to define the body transconductance as:

( typically ranging from 0.1 to 0.3) represents the ratio between the body transconductance and its gate equivalent. Its expression can be directly derived from the body effect equation, yielding:

variation.

Impact on IC design

Historically, the body effect is categorized as a non-ideal parasitic effect, introducing severe design constraints in both digital and analog design. More precisely, the most common drawbacks resulting from body biasing are:

Advanced applications and modern architectures

In modern microelectronics, the capability to intentionally modulate the threshold voltage through the substrate terminal has transformed the body effect from an unwanted parasitic phenomenon into an alternative design tool that can be intentionally exploited to improve chip design. More precisely, although typically negligible compared to the gate transconductance, the body transconductance provides a decoupled path to modulate the drain current, allowing the substrate to be leveraged as an alternative input for signal operation and control.

Back gate control in FD-SOI technologies

In fully-depleted silicon on insulator technologies (FD-SOI), the transistor channel is fabricated on a very thin layer of fully depleted silicon, which is electrically isolated from the substrate by a BOX layer (buried oxide). In this case, the substrate acts as an isolated second gate for the MOSFET and it is often referred to as back-gate.

with significantly greater efficacy than in bulk planar devices. In particular, this architecture enables dynamic body biasing (DBB), greatly boosting the efficiency of FD-SOI digital blocks through:

  • ) decreases the magnitude of the substrate effect. As a consequence the overdrive of the MOS structures increases, allowing a more conductive behavior of the devices and better switching performances of the logic gates. It is important to note that this approach is possible only when carefully taking into account the limits coming from the turn-on of the parasitic source-bulk and drain-bulk diodes of the device.

  • , mitigating the leakage subthreshold currents of the off-devices and allowing the logic blocks to enter an extremely low power standby state.

Ultra-low power (ULP) and ultra-low voltage (ULV) circuits

For applications targeting the IoT (Internet of things), implantable biomedical sensors, or energy-harvesting systems,). In this extreme regime, conventional gate-driven amplifier topologies cannot be used, as they fail to guarantee an acceptable input dynamic. To circumvent this limitation, the amplifier input signal can drive directly the body terminal of the input transistors, while their gates are biased at a constant DC voltage maintaining the devices in weak inversion condition. This approach is commonly known as bulk-driven MOSFET design and completely relies on the body transconductance, thus requiring dedicated wells to isolate the bulk of each device from the substrate of the chip. Although these topologies introduce major trade-offs, mainly due to the weaker transconductance factor with respect to the main gate action, they potentially enable wide (almost rail-to-rail) input swings while still preserving a linear operation. Some of these drawbacks can be mitigated by boosting the overall voltage gain of the stages through cascoded topologies or by applying local positive feedback techniques embedded within the input stage.

See also

References