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Wikipedia / ARM Cortex-A9

The ARM Cortex-A9 MPCore is a 32-bit multi-core processor that provides up to 4 cache-coherent cores, each implementing the ARM v7 architecture instruction set. It was introduced in 2007.

Features

Key features of the Cortex-A9 core are:

  • Out-of-order speculative issue superscalar execution 8-stage pipeline giving 8.50DMIPS/MHz/core.

  • NEON SIMD instruction set extension performing up to 16 operations per instruction (optional).

  • High performance VFPv3 floating point unit doubling the performance of previous ARM FPUs (optional).

  • Thumb-2 instruction set encoding reduces the size of programs with little impact on performance.

  • TrustZone security extensions.

  • Jazelle DBX support for Java execution.

  • Jazelle RCT for JIT compilation.

  • Program Trace Macrocell and CoreSight Design Kit for non-intrusive tracing of instruction execution.

  • L2 cache controller (0–4MB).

  • Multi-core processing.

ARM states that the TSMC 40G hard macro implementation typically operates at 2GHz; a single core (excluding caches) occupies less than 1.5mm2 when designed for a 65 nanometer (nm) generic process and can be clocked at speeds over 1GHz, consuming less than 250mW per core. Without the limit of power consumption, the A9 can reach 3.1GHz, on a proof-of-concept 28 nm chip.

Chips

Several system on a chip (SoC) devices implement the Cortex-A9 core, including:

Systems on a chip

See also

References

  1. ARM Holdings

  2. ARM Cortex-A9 Technical Reference Manuals

  3. Other

  4. White paper - The ARM Cortex-A9 Processors

  5. RISC vs. CISC in the mobile era

  6. STMicroelectronics SPEAr1310 Data brief

  7. RM Cortex-A9

  8. Popular ARM Cortex-A9 MPCore & Multi-core processor videos, YouTube.

  9. ARM Assembly language