The UltraSPARC II, code-named "Blackbird", is a microprocessor implementation of the SPARC V9 instruction set architecture (ISA) developed by Sun Microsystems. Marc Tremblay was the chief architect. Introduced in 1997, it was further development of the UltraSPARC operating at higher clock frequencies of 250MHz, eventually reaching 650MHz.

The die contained 5.4 million transistors and had an area of 149mm. It was fabricated by Texas Instruments in their 0.35μm process, dissipated 25 W at 205MHz, and used a 2.5 V power supply. L2 cache capacity was 1 to 4 MB.

In 1999, the UltraSPARC II was ported to a 0.25μm process. This version was code-named "Sapphire-Black". It operated at 360 to 480MHz, possessed a die area of 126mm, dissipated 21 W at 400MHz and the power supply voltage was reduced to 1.9 V. Supported L2 cache capacity was increased to 1 to 8 MB.

Derivatives

The UltraSPARC II was the basis for four derivatives.

UltraSPARC IIi

The UltraSPARC IIi "Sabre" featuring on-chip PCI controller was a low-cost version introduced in 1997 that operated at 270 to 360MHz. It was fabricated in a 0.35μm process and possessed a die size of 156mm. It dissipated 21 W and used a 1.9 V power supply. It had a 256 KB to 2 MB L2 cache. In 1998, a version code-named Sapphire-Red, was fabricated in a 0.25μm process, enabling the microprocessor to operate at 333 to 480MHz. It dissipated 21 W at 440MHz and used a 1.9 V power supply.

UltraSPARC IIe

The UltraSPARC IIe "Hummingbird" was an embedded version introduced in 2000 that operated at 400 to 500MHz, fabricated in a 0.18μm process with aluminium interconnects. It dissipated a maximum of 13 W at 500MHz, used a 1.5 to 1.7 V power supply and had a 256 KB L2 cache.

UltraSPARC IIe+

The UltraSPARC IIe+ or IIi was introduced in 2002. Code-named "Phantom", it operated at 550 to 650MHz and was fabricated in a 0.18μm process with copper interconnect. It dissipated 17.6 W and used a 1.7 V power supply. It had a 512 KB L2 cache.

Gemini

The Gemini was the first attempt by Sun to produce a multithreaded microprocessor. It had taped out, but was cancelled before it was introduced after the announcement of UltraSPARC T1 Niagara microprocessor in early 2004. It consisted of two UltraSPARC II cores and an on-die L2 cache on a single chip.

The DAC 2004 abstracts described the dual-core UltraSPARC II processor in Session 40. The "Dual-Core UltraSPARC (2003)" was based upon the UltraSPARC II microarchitecture and featured: DDR-1 memory controller, JBUS interface, parity protected L1 cache, ECC-protected dual 512KB on-chip L2 cache, 1.2GHz clock frequency, 80 million transistors, 206 mm die size, and dissipated 23 watts of power.

References

Further reading